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Avi Patel

06 / Independent FPGA/HLS project

PYNQ-Z2 Acceleration Suite

Designing the boundary between Python and programmable logic.

Two acceleration paths—a radix-4 Booth multiplier and a streaming 3×3 image kernel—with host interfaces and repeatable mock tests.

Source and implementation status Open browser mock
Context
Independent FPGA/HLS project
When
2026
Stage
Partial FPGA prototype
Tools & methods
HLS · AXI4-Lite · AXI4-Stream · PYNQ · Python · Image processing
PYNQ architecture linking Python control to AXI interfaces, a multiplier, and an image kernel.
Architecture from the public partial-prototype repository.

01 / Context

The problem

An accelerator needs more than a compute kernel. Data formats, control registers, streaming behavior, host drivers, and validation have to agree across the hardware/software boundary.

02 / Ownership

My contribution

I developed the HLS paths, PYNQ Python drivers, notebooks, and host or mock tests. The suite explores both a control-oriented multiplier interface and a streaming image-processing path, with remaining board work documented explicitly.

03 / Architecture

How it works

  1. 01

    Compute

    Implement a radix-4 Booth multiplier and a streaming 3×3 image/filter kernel in HLS.

  2. 02

    Connect

    Structure AXI4-Lite control and AXI4-Stream/DMA-oriented data interfaces.

  3. 03

    Drive

    Expose the paths through Python drivers and PYNQ notebooks.

  4. 04

    Test

    Use host and mock workflows to exercise interfaces before completing board validation.

04 / Validation

Evidence & scope

  • Public HLS source, drivers, notebooks, and host/mock testing workflow.
  • Repository architecture and implementation-status documentation.
  • A related browser image-inspection experiment illustrates the intended image-processing workflow.

Project scope

Synthesis results, a completed bitstream, board/DMA testing, and measured speedups remain pending. The browser image-inspection view is a mock demonstration.

Source and implementation status Open browser mock Related image experiment

05 / Perspective

Engineering takeaway

The hardware/software interface is part of the design. Separating host tests from board measurements makes it clear which behavior has been exercised and which claims still need a physical implementation.

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02 / Silicon & Compute

Digital implementation

Synthesis, physical design, timing analysis, and flow automation across two digital designs during my Cadence internship.

Genus · Innovus · Tempus · Static timing analysis

Professional experienceMay–August 2025
05 / Silicon & Compute

FPGA timing controller

A synthesizable Verilog controller coordinating a clock, alarms, stopwatch, countdown, snooze, and user inputs.

Verilog · FPGA · ModelSim · State machines

Hardware-validated team projectAcademic project