FPGA timing controller

01 / Context

The problem

A timing controller becomes interesting when several functions have to coexist. Mode changes, button bounce, rollover, and concurrent timing behavior can all expose bugs that a single happy-path demonstration misses.

02 / Ownership

My contribution

I led a three-person team on the synthesizable controller and built ModelSim testbenches for rollovers, mode transitions, and concurrent functions. The design combined debounced inputs, display control, and PWM audio, followed by validation on FPGA hardware.

03 / Architecture

How it works

1. 01

   Structure

   Separate shared timekeeping and mode-specific state so functions can coexist.

2. 02

   Interface

   Debounce user inputs and coordinate the display and audible output.

3. 03

   Exercise

   Test rollover, mode changes, and simultaneous functions in ModelSim.

4. 04

   Validate

   Check the controller's behavior on the FPGA board after simulation.

04 / Validation

Evidence & scope

• Synthesizable Verilog and simulation testbenches developed in a three-person team.
• Boundary-case checks for rollover, transitions, and concurrency.
• Controller behavior validated on FPGA hardware.

05 / Perspective

Engineering takeaway

A digital design needs a plan for state and a plan for testing that state. Boundary cases reveal more about a multi-mode controller than a demonstration of each feature in isolation.