Avi Patel
02 / Cadence Design Systems · Internship
Following a design from logic into physical constraints.
Synthesis, physical design, timing analysis, and flow automation across two digital designs during my Cadence internship.
Conceptual system sequence
A visual explanation of the workflow.
01 / Context
RTL describes a design's behavior. A realizable implementation must also account for clocking, placement, interconnect, power, area, and timing constraints. A change at one stage can shift the problem at another.
02 / Ownership
I worked through synthesis, floorplanning, placement, clocking, routing, and signoff-oriented checks. I investigated timing and physical-design behavior using constraints, reports, and physical context, and scripted recurring implementation and analysis tasks.
03 / Architecture
Connect the logical design to its clocks, timing intent, and implementation constraints.
Use Genus and Innovus through synthesis and the physical-design flow.
Use Tempus reports and physical context to trace timing behavior across the flow.
Automate repeatable setup and analysis so implementation choices can be assessed consistently.
04 / Validation
Generalized internship overview with an original educational illustration of the implementation flow.
05 / Perspective
Timing is a system-level interaction between logic, clocks, placement, and routing. A useful debugging approach follows the evidence across those boundaries and changes assumptions deliberately.